Electrostatic discharge (ESD) is a continuing problem in the design, manufacture, and utilization of integrated circuits (ICs). A major source of ESD exposure to ICs is from the human body (described by the “Human Body Model”, HBM). In this situation, a packaged IC acquires a charge when it is touched by a human who is electrostatically charged (e.g. from walking across a carpet). A charge of about 0.4 uC may be induced on a body capacitance of 100 pF, for example, leading to an electrostatic potential of 4 kV or more and discharge peak currents of several amperes to the IC for longer than 100 ns. A second source of ESD exposure is from charged metallic objects (described by the “Machine Model”, MM), which is characterized by a greater capacitance, lower internal resistance and transients that have significantly higher peak current levels than a HBM ESD source. A third source of ESD exposure is due to the discharge of stored charge on the integrated circuit itself (described by the “Charged Device Model”, CDM), to ground with rise times of less than 500 ps. The current flow during CDM is in the opposite direction of the HBM and MM ESD sources. For all three sources of ESD exposure, both positive and negative polarity discharges may occur.
Electrostatic discharge transistors may be formed on an integrated circuit chip to protect the input and output (I/O) pins of the integrated circuit or electrostatic discharge transistor circuits may be manufactured and packaged as standalone devices. The standalone ESD circuit may be placed on an integrated circuit board to protect board components from ESD events.
A circuit diagram of a conventional ESD circuit is shown in FIG. 1A. It consists of two NPN transistors, 102 and 106, with their emitters and bases coupled together. The emitter of each NPN transistor is coupled to a terminal through a forward biased diode. The emitter of NPN transistor 102 is coupled to Vss through diode 104 and the emitter of NPN transistor 106 is coupled to a pin (IN) through diode 100. When a negative ESD pulse hits IN, NPN ESD transistor 106 turns on and current is discharged from IN in series through forward biased diode 100 and NPN transistor 106. When a positive ESD pulse hits IN, NPN ESD transistor 102 turns on and current is discharged from IN in series through forward biased diode 104 and NPN ESD transistor 102.
The clamp voltage of the conventional ESD circuit in FIGS. 1A and 1B is the clamp voltage of the NPN ESD transistor plus the clamp voltage of the diode which is in series (Vclamp_NPN+Vclamp_diode). Series diodes 100 and 104 must be sufficiently large to handle the largest ESD strikes that may occur. If the diodes, 100 and 104, are not sufficiently large, the forward biased diode voltage may rise above what is safe for the integrated circuit due to current crowding and destroy the integrated circuit.
As shown in the top down layout of the integrated circuit in FIG. 1B, the conventional ESD transistor circuit in FIG. 1A may consume considerable silicon area. The first NPN ESD transistor 102 consists of an n-type emitter diffusion 112 and an n-type collector diffusion 114 separated by a strip of p-type base. Silicide may be blocked from a portion of the collector diode 114 as is indicated by dashed region 115. The second NPN ESD transistor 106 consists of an n-type emitter diffusion 116 and an n-type collector diffusion 118 separated by a strip of p-type base. Silicide may be blocked from a portion of the collector diode 118 as is indicated by dashed region 115. P-type diffusions form substrate contacts, 108 and 110, to the base of the NPN ESD transistors 102 and 106. P/N diodes 100 and 104 are formed of multiple alternating n-type diode diffusions 117 in an isolated pwell and isolated pwell contacts 119. The diodes 100 and 104 are formed in isolated pwells which are separate from the isolated pwells in which the NPN transistors 102 and 106 are formed.